Amit Jain

Contact Information:

EECS
1301 Beal Avenue
Ann Arbor, MI 48109-2122
amjain@umich.edu

 

Research Interest:

VLSI CAD 
Timing analysis

Current Research:

I am currently working on modeling the variable flip-flop delays in timing analysis. It has been known that as the arrival time for a flip-flop goes closer to the clock the delay of the flip-flop increases. This variable delay if modeled can be used to decrease the clock period of a design. This can also be used to decrease the clock period for a latch-based design. I am also looking at some new flip-flop designs.