Aseem Agarwal

Aseem Agarwal

Contact Information:

1301 Beal Avenue
Ann Arbor, MI 48109-2122
Ph: 7347093779
[email protected]

Research Interest:

CAD for VLSI. Timing Analysis Models and Algorithms. Statistical Timing Analysis considering Process Variations. Statistical gate delay and process variation models. Circuit Optimization considering statistical variations

Current Research:

In recent technologies, the variability of circuit delay due to process variations has become a significant concern. As process geometries continue to shrink, the ability to control critical device parameters is becoming increasingly difficult, and significant variations in device length, doping concentrations, and oxide thicknesses have resulted. Traditional corner analysis has been successfully used in the past to model die-to-die variations, however, it is not able to accurately model variations within a single die. Hence, there is a need for a Statistical Static Timing Analysis(SSTA) tool. 

Our work on Statistical SSTA includes the following topics: 

1. Path-Based SSTA 
2. Block-Based SSTA 
3. Statistical Clock Skew Analysis 

Our recent work includes mathematical and algorithmic solutions for handling reconvergence and spatial correlations while performing Block-Based SSTA. Also, we provided efficient solutions for determining the  Skew distribution of a clock tree. (ICCAD 2003) 

Future work includes incorporating slope and loading effects into the SSTA framework, and performing Statistical Optimization of the circuit to improve the Statistical Timing Yield.