Contact Information:
EECS
1301 Beal Avenue
Ann Arbor, MI 48109-2122
Ph: 734-763-6466
[email protected]
Research Interest:
Low power design and related optimization/statistical issues
Current Research:
Power dissipation is expected to be a major bottleneck in the development of high-performance microprocessors and mobile applications. We are developing techniques to optimize power in multiple supply and threshold voltage designs under performance constraints. Development of new techniques and algorithms/tools that allow the new approach to be integrated into a design flow would be extremely beneficial. Process Variation is also becoming a larger concern, as variations do not seem to be scaling at the same rate as process technology. To prevent excessive guard banding which leads to un-optimized designs, we need to be able to model device characteristics statistically, due to the inherent probabilistic nature of process variation. Further analysis on these models can be used to develop techniques which will allow us to control the effect of process variation. Currently we are working on developing techniques and algorithms to optimize power dissipation considering effects of process variations.