Low power CMOS digital design. Circuit techniques to reduce overall off-state current due to subthreshold leakage and gate tunneling current. Circuit techniques for run-time leakage reduction
Currently, I am working towards developing methods to reduce the overall off-state current in modern sub-micron devices. Subthreshold leakage has been known to be a problem for quite some time, however, as devices are further scaled, gate tunneling current is a major concern in sub-100nm device design. I am looking at techniques to reduce both these currents at a device and circuit level. Techniques such as multi-threshold circuits as well as power gating (inserting sleep devices) and multi-oxide processes are being investigated to find a method which effectively reduces overall leakage.