Hyunwon Chung

Contact Information:

2431 EECS 1301 Beal Avenue Ann Arbor, MI 48109-2122 [email protected]


Research Interest:

Hardware/Software Co-design
Domain Adaptive Processor
Low-power Circuit Design

Current Research:

Coarse-grained Reconfigurable Architecture (CGRA) for communication and machine learning

Traditional dedicated accelerators excel in performing predefined tasks with high efficiency;
however, their capability to adapt and transition between varied tasks rapidly is significantly
constrained. This limitation becomes particularly critical in applications requiring real-time
adaptability, such as signal processing in communication systems, where the need for
dynamic kernel reconfiguration based on signal detection is essential.

Addressing this challenge, my current research is focused on the design of Coarse-Grained
Reconfigurable Architecture (CGRA) specifically for streaming-data processing and real-
time reconfiguration capabilities. By reimagining the architecture of these processors, our
goal is to transcend the adaptability limitations of conventional accelerators, enabling them to
modify their operational functions on-the-fly without sacrificing efficiency.