Contact Information:
2431 EECS 1301 Beal Avenue Ann Arbor, MI 48109-2122 [email protected]
Research Interest:
Processor Design, Accelerator Design, Hardware-Software Co-Design
Current Research:
Coarse-Grained Reconfigurable Architecture (CGRA) Design for Signal Processing/Machine Learning Applications
Systolic array-based accelerators are precisely designed for a specific application and therefore
lack reconfigurability. My current research involves designing a CGRA accelerator to support
efficient parallel execution of multiple kernels with dynamic reconfigurability.