1301 Beal Avenue
Ann Arbor, MI 48109-2122
Low-power Memory Design (SRAM, Flash, MRAM)
Low-power variation-tolerant STT-MRAM Design (28nm)
- Proposed a single-cap offset-cancelled sense amplifier;
- Proposed an in-situ self-termination write method to save write power;
- Taped out in 28nm MRAM technology.
1W2R 4+2T SRAM/CAM/Logic-in-Memory Design (55nm)
- Proposed a 4+2T SRAM cell with decoupled read ports and N-Well based write wordline, achieving 0.25V VDDmin and >5σ write margin;
- The decoupled RWLs and RBLs can be reconfigured for BCAM/TCAM and bitwise logic operations (AND/OR/XOR);
- Taped out in 55nm DDC technology.
Low-power NOR Flash Design for Sensor Node Application (90nm)
- Proposed cross-sampling margin-doubled current sense amplifier, achieving 11ns read cycle and 0.72V read VDDmin;
- Proposed highly power-efficient charge pump for 13V generation with 73% peak efficiency;
- Taped out 1Mb & 8Mb NOR Flash in 90nm ESF3 technology, achieving sub-100μW program and erase power from -25⁰C to 125⁰C.
Sub-nW Variation-tolerant Voltage Reference (180nm & 90nm)
- Proposed PMOS-only, trim-free voltage reference generator achieving 0.26% within-Wafer inaccuracy, 48-124ppm/°C temperature coefficient from −40°C to 85°C, and 114pW power consumption;
- Taped out in 180nm and 90nm technology.
4Mb Low-power 5T SRAM Design for Face-recognition DSP (40nm)
- Proposed a 5T SRAM cell with a decoupled read path, 7.2% less area than conventional 6T SRAM;
- Designed low power peripheral circuits for the read, achieving 38% less read energy than 6T and improving VDDmin to 0.5V at 100MHz for 4Mb Macro;
- Taped out in 40nm technology.
Design with Emerging Spintronic Devices
- Developed Verilog-A models of MTJ, domain wall and racetrack nanowire;
- Propose an 8b low power racetrack ADC structure with extreme compact area;
- Applied the racetrack ADC for high-speed digital pixel image sensor application;
- Proposed spin based rectified-linear and recurrent neural network for inference applications.