Rajeev Rao

Contact Information:

4844 CSE
2260 Hayward Avenue
Ann Arbor, MI 48109-2122
Ph: 734-763-3309

Research Interest:

Modeling and analysis of low-power VLSI systems considering multiple sources of uncertainty. These include 
– Full-chip statistical leakage current analysis and parametric yield estimation considering the leakage/performance correlation 
– Low-power interconnect design combined with buffer planning for global busses (using bus encoding) as well as local signal nets (using power-aware buffer insertion) 
– Soft error rate analysis for combination logic circuits and the development of circuit-level mitigation techniques.

Current Research:

My current research involves the development of power and area efficient soft error rate (SER) mitigation techniques for combinational logic circuits. Traditional radiation hardening methods that rely on replicate/recompute mechanisms (such as triple modular redundancy) as well as those that involve space/time redundancy incur huge power/delay overheads. My current work proposes the identification of a select few SER-critical gates and provides a method to only harden this subset of the total gates to achieve significant SER reduction. 

I’m also working on another project that examines the impact of input vector stimulus on the current distribution of logic blocks. My current objective in this work is to develop an efficient method to design power delivery systems considering the impact of these current signature at both local and global levels of the chip design.