Ravikishore Gandikota

Ravikishore Gandikota

Contact Information:

4844 CSE
2260 Hayward St.
Ann Arbor, MI 48109-2121
Ph: 734-358-7268
Fax: 734-763-4617
[email protected]

Research Interest:

VLSI Design & Automation

Current Research:

Enumerating the Top-k Aggressors Sets in Delay Noise Analysis [dac07] 
An efficient algorithm was proposed to enumerate the top-k critical aggressors which contribute maximally to the delay noise of a circuit.  The reported set of top-k aggressors can be fixed to eliminate delay noise violations. 

Victim Alignment for Worst-Case Delay Noise [iccad07] 
We analytically prove that the worst-case delay noise is obtained when the victim transition is aligned at the latest point in its timing window. The result holds even with non-linear victim-aggressor drivers and multiple aggressors. 

Statistical Crosstalk Analysis [dac08] 
Closed-form expressions were derived to compute the mean and standard deviation of delay noise distribution. The correlations of the delay noise were also computed to obtain the canonical delay noise distribution which could be easily integrated with existing SSTA tools. 

Worst-Case Interconnect Corner considering Capacitive Coupling [under review] 
All prior approaches which predict the worst-case interconnect corner do not distinguish between the wire coupling capacitances and the wire ground capacitance. In this work, we compute the worst-case interconnect corner by also accounting for the effects of crosstalk noise. 

Worst-Case Aggressor Alignment with Non-linear CSMs [tau09] 
A heuristic method was developed to find the worst-case aggressor-victim alignment considering non-linear CMOS aggressor-victim drivers. The worst-case aggressor alignment was computed such that it maximizes the arrival time at the victim receiver output. 

Pessimism Reduction with Path-based Crosstalk Noise Analysis [patent filed] 
An approach was developed to reduce the pessimism associated with the worst-case alignment of the aggressors in path- based crosstalk noise analysis. 

Statistical Design Optimization 
A statistical timing optimizer was implemented and integrated with an industrial SSTA tool which used a cut-set based approach to compute the statistical sensitivities. Several novel techniques were implemented to improve the runtime of the optimizer.