Sechang Oh

Sechang Oh

Contact Information:

2435 EECS
1301 Beal Avenue
Ann Arbor, MI 48109-2122


Research Interest:

Low power circuit design

Current Research:

15.4b Incremental Sigma-Delta Capacitance-to-Digital Converter with Zoom-in 9b Asynchronous SAR 
By using a 9b SAR, the OSR can be reduced to only 32, significantly improving conversion energy. OTA in the SAR is bypassed for the CDC further reducing energy and propose a novel matrix based 512-element unit-cap structure for dynamic element matching. The CDC achieves 94.7dB SNR and 33.7μW power consumption with 175fJ/conv-step at 1.4V supply. 

Dual-Slope Capacitance to Digital Converter Integrated in an Implantable Pressure Sensing System 
The design uses base capacitance subtraction with a configurable capacitor bank and dual precision comparators to improve energy efficiency, consuming 110nW with 9.7b ENOB and 0.85pJ/conv•step FoM. The converter is integrated with a pressure transducer, battery, processor, and radio to form a complete 1.4mm×2.8mm×1.6mm sensor system aimed at implantable devices. The system operates from a 3.6V battery.