I am interested in circuit design techniques for circuit level timing speculation. I am also interested in interconnect modeling and exploring techniques to exploit onchip inductance to design faster interconnects.
Currently, I am working on developing low overhead circuits for “Razor” which is a novel dynamic voltage scaling technique. I have designed a novel flipflop called the “razor” flipflop which allows operation under subcritical voltage regimes by efficiently detecting and correcting speed path failures. Thus, in the razor technique, supply voltages can be reduced to levels much lower than what is possible in standard DVS techniques. Hence, energy savings from razor can be potentially much greater than traditional DVS.
We have also designed a “Razor” prototype to demonstrate this technique in silicon. This chip is currently under fabrication and will be available for testing in February-March 2004.