Contact Information:
2435 EECS
1301 Beal Avenue
Ann Arbor, MI 48109-2122
Ph: 2488509974
[email protected]
Research Interest:
Low power/High performance VLSI design,
Wear out detection due to NBTI and Hot carrier injection
Current Research:
Low power GPS systems:
GPS systems involve massive correlation. Conventional techniques using pipelined adders to compute correlation end up consuming significant clock power by using 18000-50000 flip flops depending on degree of pipelining. Replacing flip flops with latches reduces clock load to half but generates large number of short paths giving rise to hold time violations. Inserting buffers to meet hold constraints again consumes power.
We are looking into mixed signal approaches to compute correlation which could eliminate the need for having latches/flip flops and hence consume minimal clock power and still get the same reliable performance.