1301 Beal Avenue
Ann Arbor, MI 48109-2122
Low Power Digital Circuits, Interconnect Fabrics and Memory Design.
– Scalable, energy-efficient interconnect fabric with built-in arbitration protocols is required for Exa-scale computing. My research involves designing 3Dtopologies for switches, to decrease the interconnect fabric’s area, power and latency while still maintaining the fairness and bandwidth.
– Configurable memory including content addressable memory and memory based computing.
– Low power non-volatile memory design