Sensors with long lifetime are becoming increasingly popular in areas such as medical, infrastructure, and environmental monitoring. In sensor applications, reducing the standby power consumption is as important as reducing the active power consumption since the sensors spend significant time in standby mode. To minimize the standby power consumption, designing low leakage memory is indispensible. Often, the leakage power consumption from memories dominates the total standby power consumption, since data stored in memory must be retained while most other blocks such as CPU, radios, and sensors can be fully power gated.
A low leakage 14T SRAM cell with stacked HVT devices was previously proposed; however, its area is 9.1X larger than the traditional 6T cell and the HVT devices degrades write performance by more than 10X compared to the read speed. To overcome these limitations and to further reduce leakage, this work proposes a new ultra low leakage SRAM, referred to as the low leakage 10T SRAM which has the lowest leakage/bit reported to-date.
We show how the boosted supply can increase operation speed and reduce leakage power simultaneously. Sensor applications typically operate using batteries, such as thin film batteries which tend to have high supply voltages. To obtain the subthreshold operating voltages, a common method for DC-DC conversion is to use a switched-capacitor networks (SCN) followed by a low-dropout regulator (LDO). In this case, boosted supply can be obtained with minimal overhead since it can be directly obtained from the input of the LDO or from a higher voltage output from the ladder SCN. Also, several circuit techniques, including a floating bit-line scheme, word-line keeper, and read buffer, are introduced to reduce leakage further and guarantee robust read and write operation.
A prototype chip, which has 24kb of the low leakage 10T SRAM, shows that a bit-cell consumes 1.85fW of standby power at 0.35V with 0.5V of boosted supply. To our knowledge, this marks the lowest-to-date SRAM leakage power. The bit-cell area is 17.48um^2 which is 3.97X larger than a traditional 6T cell but 2.3X smaller than the previous low leakage 14T SRAM. Since logic design rules are used in this design, area overhead can be mitigated with pushed SRAM design rules. This SRAM is successfully demonstrated as a part of an integrated sensor system with a CPU, power management unit, solar cells, and battery.
A 1.85fW/bit Ultra Low Leakage 10T SRAM with Speed Compensation Scheme
Daeyeon Kim, Gregory Chen, Matthew Fojtik, Mingoo Seok, David Blaauw, Dennis Sylvester, “A 1.85fW/bit Ultra Low Leakage 10T SRAM with Speed Compensation Scheme,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2011 ©IEEE