Dual Vt, Dual Vdd and sizing optimization

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Ashish Srivastava    ansrivas@eecs.umich.edu

We have developed a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment.  The algorithm runs in two distinct phases. The first phase relies on upsizing to create slack and maximize low Vdd assignments in a backward topological manner. The second phase proceeds in a forward topological fashion and both sizes and re-assigns gates to high Vdd to enable significant static power savings through high Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. A comparison with traditional CVS and dual-Vth/sizing algorithms demonstrate the advantage of the algorithm over a range of activity factors, including an average power reduction of 37% (58%) at primary input activities of 0.1 (0.01). We also investigate the impact of level conversion delay, tightness of timing constraints, and various low Vdd and Vth values on total power savings.

Publications:

Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design

Ashish Srivastava, Dennis Sylvester, David Blaauw, “Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design,” ACM/IEEE Design Automation and Test in Europe Conference (DATE), Vol. 1, February 2004, pg. 718-719. ©IEEE

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