Efficient Design Techniques for Inductance Dominated Interconnect Structures


Primary Contact

Kanak Agarwal    kba@us.ibm.com

Inductance has some desirable properties that can be exploited. We have investigated the concept of an optimal inductance value that can substantially reduce delay of global RLC signals while maintaining good signal integrity (low ringing/overshoot).  We exploit the fact that inductance results in faster transition times to improve delay of buffers in global signal lines. We observe that voltage overshoot, slew rate, and total line delay all show strong inflection points at the same value of inductance. At this optimal value of inductance significant improvements in signal transition time, and hence in overall signal delay, are obtained with negligible ringing. We propose adjusting the power grid to achieve this optimal inductance. Results show that the delay of a 1cm line with 9 inserted repeaters can be reduced by 8-12% with acceptable ringing by operating at the optimal inductance point. 

Inductance degrades signal integrity due to signal overshoot and ringing. We have developed a novel approach called dynamic clamping for minimizing crosstalk noise and inductive effects in global buses. A simple circuit is proposed that can be used to dynamically shield and terminate high-speed RLC buses. Unlike traditional passive shielding and parallel termination, dynamic clamping has no area overhead and no static power dissipation. Dynamic clamping enables significant reductions in noise and inductive overshoot with a small delay penalty.


Dynamic Clamping: On-Chip Dynamic Shielding and Termination for High-Speed RLC Buses

Kanak Agarwal, Dennis Sylvester, David Blaauw, “Dynamic Clamping: On-Chip Dynamic Shielding and Termination for High-Speed RLC Buses,” IEEE International Symposium on System-on-Chip, November, 2003, pg. 97-100. ©IEEE