Power consumption and propagation delay of long on-chip buses are two very important design criteria in high-speed digital designs. In particular, the runtime leakage power associated with buffers on long buses has grown to an unacceptable portion of the total power budget and become a major concern. In this paper, we propose a new bus encoding algorithm and circuit scheme for onchip buses that eliminates capacitive crosstalk while simultaneously reducing total power, defined as the sum of dynamic and static components. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. We show that the proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.
Bus Encoding for Total Power Reduction using a Leakage-Aware Buffer Configuration
Rajeev Rao, Harmander Deogun, David Blaauw, Dennis Sylvester, “Bus Encoding for Total Power Reduction using a Leakage-Aware Buffer Configuration,” IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Vol. 13, Issue 12, Dec. 2005, pg. 1376-1383 . ©IEEE File: [PDF Document]
Crosstalk- and Leakage-Aware Bus Encoding for Total Power Reduction
Harmander Deogun, Rajeev Rao, Dennis Sylvester, David Blaauw, “Crosstalk- and Leakage-Aware Bus Encoding for Total Power Reduction,” ACM/IEEE Design Automation Conference (DAC), June 2004, pg. 779-782. ©IEEE File: [PDF Document]