Low Power Chip Multi-processing using Near Threshold Voltage Techniques



Primary Contact

Bo Zhai <bzhai@umich.edu>

Energy consumption has drawn a lot of attention in portable electronics recently.  One of the most effective approaches in energy efficient design is to operate in subthreshold regime. However, this introduces significant performance degradation. In this research, we investigated the possibility of applying multi-processing for medium performance applications and show that near threshold voltages operation are energy optimal. By carefully choosing the Vdd and Vth, we can easily operate the processor core and the caches at different speed including running L1 caches faster than the cores and having several cores sharing one L1. Under a certain performance/throughput constraint, we have analyzed different core and caches speed/power tradeoff with their respective Vdds and Vths. Also we have investigated the optimal number of clusters for various performance requirements.


Energy Efficent Near-threshold Chip Multi-processing

Bo Zhai, Ronald G. Dreslinski, Trevor Mudge, David Blaauw, Dennis Sylvester, “Energy Efficent Near-threshold Chip Multi-processing,” ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED), August 2007, Best Paper Nomination ©IEEE