Modeling and Analysis of Inductive Effects in VLSI Interconnects



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Kanak Agarwal

With inductance, driver output waveforms are no longer smooth as in RC cases. Due to such nature of the waveforms, the conventional driver output modeling approaches are highly inaccurate as they fail to capture inductive effects. We have developed a new modeling methodology to gate-level timing characterization in the presence of RLC interconnect loads. The approach is based on transmission line theory and it accurately predicts both the 50% delay and waveform shape (slew rate) at the driver output when inductive effects are significant. The proposed approach does not rely on piecewise linear Thevenin voltage and is compatible with existing library characterization methods. 

Most existing noise models and avoidance techniques consider only capacitive coupling. However, at current operating frequencies inductive crosstalk effects can be substantial and should be included for complete coupling noise analysis. We have developed a RLC crosstalk noise model that combines simplicity, accuracy, and generality. The new model is applicable to asymmetric driver and line configurations. The model is applied to investigate the impact of various physical design optimizations (e.g., wire sizing and spacing, shield insertion) on total RLC coupled noise. Results indicate that common (capacitive) noise avoidance techniques can behave quite differently when both capacitive and inductive coupling are considered together.


A Library Compatible Driver Model for On-Chip RLC Transmission Lines

Kanak Agarwal, Dennis Sylvester, David Blaauw, “A Library Compatible Driver Model for On-Chip RLC Transmission Lines,”  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), Volume 23,  Issue 1,  Jan. 2004, pg. 128 – 136. Short paper ©IEEE