Students:
Primary Contact
Aseem Agarwal [email protected]
In recent technologies, the variability of circuit delay due to process variations has become a significant concern. As process geometries continue to shrink, the ability to control critical device parameters is becoming increasingly difficult, and significant variations in device length, doping concentrations, and oxide thicknesses have resulted. Traditional corner analysis has been successfully used in the past to model die-to-die variations, however, it is not able to accurately model variations within a single die. Hence, there is a need for a Statistical Static Timing Analysis(SSTA) tool.
Our work on Statistical SSTA includes the following topics:
1. Path-Based SSTA
2. Block-Based SSTA considering reconvergence
3. Block-Based SSTA w/ reconvergence and spatial correlations
Publications
Statistical Timing Analysis Using Bounds and Selective Enumeration
Aseem Agarwal, Vladimir Zolotov, David Blaauw, “Statistical Timing Analysis Using Bounds and Selective Enumeration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), Vol. 22, No. 9, September 2003, pg. 1243-1260 ©IEEE File: [PDF Document]
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Aseem Agarwal, David Blaauw, Vladimir Zolotov, “Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations,” ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2003, pg. 900-907. ©IEEE File: [PDF Document]
Computation and Refinement of Statistical Bounds on Circuit Delay
Aseem Agarwal, David Blaauw, Vladimir Zolotov, “Computation and Refinement of Statistical Bounds on Circuit Delay,” ACM/IEEE Design Automation Conference (DAC), June 2003, pg. 348-353 ©IEEE File: [PDF Document]
Statistical Timing Analysis Using Bounds
Aseem Agarwal, Vladimir Zolotov, David Blaauw, “Statistical Timing Analysis Using Bounds,” ACM/IEEE Design Automation and Test in Europe Conference (DATE), March 2003, pg. 62-67 ©IEEE File: [PDF Document]
Statistical Delay Computation Considering Spatial Correlations
Aseem Agarwal, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhou, Kaushik Gala, Rajendran Panda, “Statistical Delay Computation Considering Spatial Correlations,” ACM/IEEE Asia-Pacific Design Automation Conference (ASP-DAC), January 2003, pg. 271-276, Best Paper Award ©IEEE File: [PDF Document]