In nanometer-scale CMOS, process parameter variations have taken on increasing importance. Modern CAD tools are therefore moving towards a probabilistic view of circuit timing behavior instead of using simple corner models that capture worst-case behavior at the device level and lead to large guardbands. The current approach in probabilistic timing analysis is to perform statistical static timing analysis by modeling gate delay as a function of process parameters and propagating these distribution functions (traditional SSTA). This approach cannot easily model non-standard distributions in circuit arrival time. Also, a number of modeling issues are still in early stages of development, such as combined analysis of large interconnect structures driven by non-linear drivers, coupling events, and modeling of transparent latches. A fully mature traditional SSTA tool, capable of performing timing sign-off, is unlikely to be widely available in the near future.
Our research on statistical sampling under variability attempts to capture the exact timing behavior of circuits under increasing process variation. The goal is to make Monte Carlo based SSTA a powerful alternative for timing analysis. The focus is on developing techniques to generate samples in the process variation space with the aim of capturing maximum information about the circuit timing behavior with minimum samples. These samples can then be used for a Monte Carlo analysis to generate accurate timing models for the circuit. We have proposed a Criticality Aware Latin Hypercube Sampling (CALHS) approach to stratify the process variation space based on critical paths in the circuit and then intelligently select samples in the space. The result is that many fewer samples (up to 7X on the benchmark circuits studied) are needed to arrive at comparable accuracy in timing estimation compared to a random sampling approach. Also, in comparing a Monte Carlo-based SSTA to traditional SSTA approaches, we find over 50% less error in higher percentile delays using CALHS, even with a moderate number of samples.
Our current direction is to further improve the speedup of smart sampling for timing analysis and establish its superiority over traditional SSTA. We are also extending the application of smart sampling techniques for Statistical Optimization and Incremental Timing Analysis of Digital Circuits.