Sanjay Pant firstname.lastname@example.org
Power supply integrity analysis is extremely crucial for modern high performance designs. Power supply to the onchip devices exhibits fluctuations depending on the input vector patterns and varies considerably over time and area of the chip. In this work, we propose an approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes. The power supply network is modelled as a linear network and the statistical parameters of block currents are propagated through the linear system to obtain the mean and standard deviation of the voltage drops at any node in the grid. Both spatial as well temporal correlations between different blocks are incorporated in the analysis. The run time is linear with the length of the current waveforms which can be obtained by simulating the individual blocks for millions of cycles in Powermill/Verilog at the gate level. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its effectiveness.