A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency and optimal voltage and evaluate the need for adaptive control. The processor reaches maximum energy efficiency at 360mV, consuming 2.6pJ/Inst at 833kHz. The minimum energy consumption of the core marks a 10X improvement over previous sensor processors at the same MIPS.
Bo Zhai, Leyla Nazhandali, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, David Blaauw, Todd Austin, “A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency,” IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2006. ©IEEE