Ultra-Low Power Level Conversion


Primary Contact

Yejoong Kim [email protected]

Low-voltage circuit design has been widely investigated for ultra-low power applications, reaching as low as subthreshold level in a multi-pipelined processor, and requiring wide-range level conversion (LC) for communication with I/O pads and high-voltage circuit blocks and battery. However,  level conversion is challenging at reduced voltages since conventional approaches suffer from severe contention between weak pull-down devices and strong pull-up devices, making them vulnerable to PVT variations. 

The conventional DCVS LC suffers from a two-sided constraint on the pull-up device: if the pull-up is too weak, the pull-up transition becomes slow and the node may not be kept high, giving rise to performance/robustness issues; if the pull-up is too strong, the NMOS cannot overcome it and the circuit fails. In simulations, it fails with as little as 2-sigma VTH variation which can easily occurred in the subthreshold regime. Although various approaches have been proposed to overcome these issues, they have focused on reducing the pull-up strength thus making it too slow to charge up the internal nodes, or to strengthen the pull-down strength with huge NMOS devices thus causing large leakage currents. A dynamic approach can solve the robustness problems at the cost of high power and complicated synchronization circuits, which is not desirable for low-power applications. 

Ultra-Low Power Level Conversion

We propose a new approach called Limited Contention Level Converter (LCLC or LC2). The key idea is changing the pull-up strength depending on its operation mode. Before rising/falling transitions, only a weak keeper device keeps the internal node high (strong pull-up devices are off) so that the pull-down devices can easily overcome the weak contention at the beginning of the transition. Once the pull-down device overcomes the weak keeper, it triggers a positive feedback, followed by turning on the strong pull-up devices, resulting in a fast charging/discharging speed. Thus, LC2 does not only provide much reduced contention at the initial transition (achieving very good robustness), but it also provides fast speed during the transition (achieving very high speed). The limited contention does not require huge pull-down devices (achieving low leakage current). 

We fabricated LC2 (and DCVS LC for comparison) in 130nm CMOS. It is designed for 0.3V to 2.5V conversion. LC2 shows 3.2x faster speed at room temperature and degrades in speed by only 18% over a wide temperature range, also guaranteeing robust operations over -20°C ~ 100°C. In comparison, DCVS LC shows 104% degradation in speed and does not show the full functionality at low temperatures (<10°C). LC2 has 15x lower static power (due to the smaller pull-down devices) and 4.9x lower active power (due to the limited contention) compared to DCVS LC. LC2 has 6x smaller standard deviation in delay, demonstrating the robustness to variations. Although LC2 has more devices, the much smaller pull-down devices results in a smaller layout-size than DCVS LC.


LC2: Limited Contention Level Converter for Robust Wide-Range Voltage Conversion

Yejoong Kim, Dennis Sylvester, and David Blaauw, “LC2: Limited Contention Level Converter for Robust Wide-Range Voltage Conversion,” IEEE Symposium on VLSI Circuits (VLSI-Symp), June 2011. ©IEEE