Yoonmyung Lee <firstname.lastname@example.org>
Recent work in ultra-low-power sensor platforms has enabled a number of new applications in medical, infrastructure, and environmental monitoring. Due to their limited energy storage volume, these sensors operate with long idle times and ultra-low standby power ranging from 10s of nW down to 100s of pW. Since radio transmission is relatively expensive, even at the lowest reported power of 0.2mW, wireless communication between sensor nodes must be performed infrequently. Accurate measurement of the time interval between communication events (i.e. the synchronization cycle) is of great importance. Inaccuracy in the synchronization cycle time results in a longer period of uncertainty where sensor nodes are required to enable their radios to establish communication, quickly making radio dominate the energy budget. Quartz crystal oscillators and CMOS harmonic oscillators exhibit very small sensitivity to supply voltage and temperature but cannot be used in the target application space since they operate at very high frequencies and exhibit power consumption that is several orders of magnitude larger (>300nW) than the needed idle power. A gate-leakage based timer was proposed that leveraged small gate leakage currents to achieve power consumption within the required budget (< 1nW). However, this timer incurs high RMS jitter (1400ppm) and temperature sensitivity (0.16%/ºC).
The plain gate leakage based timer has a high uncertainty since it is triggered with a low gain Schmitt trigger and it has a long period (~10s). To combat this, we introduce: 1) a multistage structure with a high-gain triggering buffer, 2) boosted capacitance charging, 3) the use of zero threshold voltage transistor (ZVT) for faster discharge and 4) closed-loop temperature compensation to reduce temperature sensitivity. Measured results show that as the number of stages increases, duty cycle (the ratio of charging time to timer period) decreases, increasing voltage swing and reducing jitter by up to 8.1×. Total power consumption was 660 pW for this timer. We achieve temperature sensitivity compensation by exploiting the opposing temperature dependencies of gate leakage in ZVT and PMOS during the charging state and temperature sensitivity could be lowered down to 31 ppm / ºC .
“Synchronization of Ultra-Low Power Wireless Sensor Nodes
Yoonmyung Lee, Dennis Sylvester, David Blaauw, “Synchronization of Ultra-Low Power Wireless Sensor Nodes”, IEEE Internatioal Midwest Symposium on Circuits and Systems (MWSCAS), August 2011 Invited Paper ©IEEE
[PDF]A 660pW Multi-Stage Temperature Compensated Timer for Ultra-Low-Power Wireless Sensor Node Synchronization
Yoonmyung Lee, Bharan Giridhar, Zhiyoong Foo, Dennis Sylvester, David Blaauw, “A 660pW Multi-Stage Temperature Compensated Timer for Ultra-Low-Power Wireless Sensor Node Synchronization,” IEEE International Solid-State Circuits Conference (ISSCC), February 2011 ©IEEE