1301 Beal Avenue
Ann Arbor, MI 48109-2122
On-chip Signaling Techniques, High-performance and low-power circuit design, Clock Distribution, Signal Integrity and Reliability issues for nanometer VLSI design
Technology scaling has resulted in lower gate delays with every process generation. However, interconnect delays have not been scaling. This problem is exacerbated by increasing clock frequencies (which have been scaling even faster than device delays) and growing die sizes. Global communication between various functional units on a die is thus a key performance challenge for current and future technology generations. The modern paradigm to address the speed requirements of global communication is to insert large static CMOS inverters (called repeaters) periodically along the line. The growing numbers of repeaters needed to meet timing constraints have caused the power consumed in transmitting data between functional units to become a significant portion of the total chip power. This has implications not just for low power applications (where average power is the figure of merit) but also for high performance applications. There is a compelling need for new signaling strategies that either improve performance without having a major impact on power or reduce power consumption with a minimal impact on performance. Reduced spacing between signal lines has resulted in increased coupling (capacitive and inductive) between signal lines, which in turn impacts performance and signal integrity. Increased slew rates have increased the inductive nature of critical nets such as clocks. The increased inductive nature has resulted in unwanted effects like ringing that impact reliability. Any alternate signaling strategy beyond repeater insertion must therefore consider these robustness issues.
My research is aimed at circuit and signaling techniques to tackle one or more of the problems (mentioned above) associated with global on-chip signaling. I have completed work on Transition Aware Global Signaling (TAGS) and Active Shielding. The former is aimed at low-power designs, while the latter is aimed at improving performance and robustness. I am currently working on efficient bus encoding circuits and techniques to reduce power consumption with minimal impact on performance. These techniques have been previously looked at only from a power reduction perspective without any consideration of performance impact. We will identify encoding circuits and techniques and the design space where they would be efficient from an energy-delay perspective.