Sanjay Pant

Research Interest:

Power delivery, signal integrity, low-power design

Current Research:

Project Name/Title: Dynamic Power Supply Noise Suppression 

Description/Abstract: 
We developed an active decap circuit that significantly increases the effectiveness of decap in suppressing power supply fluctuations. The proposed circuit senses the supply drop and drives an amplified and inverted voltage fluctuation on the decap. The active decoupling circuit is powered by an external power supply. We studied the optimal allocation of the total C4s/pads between this external power supply and the regular supply, as well as the optimal allocation of the total decoupling capacitance between actively switched and traditional passive decap. Using the proposed method, the maximum supply drop is reduced by 45% compared to the use of only traditional decap, corresponding to an increase in the effective decap of approximately 8X at the resonance frequency. 
Our recent work involves investigation and design of more effective active voltage regulator-based techniques for improving the robustness of supply voltage to high frequency load-current transients. 

Sponsor: Intel PhD foundation fellowship 

Publications: 
Sanjay Pant, David Blaauw, “An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks,” in ACM/IEEE International Conference on Computer Design (ICCD), October 2006. 

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Project Name/Title: Decap Optimization in Power Supply Networks 

Description/Abstract: 
Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power supply noise, thus making the supply network more robust in presence of large switching currents. Traditionally, decaps have been allocated in order to minimize the worst-case voltage drop occurring in the power grid. We developed an approach for timing-aware decap allocation which uses global timing slacks to drive the decap optimization. The approach is based on the observation that in a circuit, the non-critical gates with larger timing slacks can tolerate a relatively higher supply voltage drop as compared to the gates on the critical paths. The decap allocation is formulated as a non-linear optimization problem using Lagrangian relaxation, and modified adjoint method is used to efficiently obtain the sensitivities of objective function to decap sizes. A fast path-based heuristic was also implemented and compared with the global optimization formulation. Compared to uniformly allocated decaps, the proposed approach utilizes 35.5% less total decap to meet the same delay target. For the same total decap budget, the proposed approach is shown to improve the circuit delay by 10.1% on an average. 

Sponsor: Intel PhD foundation fellowship 

Publications: 
Sanjay Pant, David Blaauw, “Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks,” in ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), January 2007. 

Sanjay Pant, David Blaauw, “Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks,” in ACM/IEEE International Workshop on Timing in Synthesis and Specification (TAU), February 2006.