Contact Information:
EECS 2003
1301 Beal Avenue, EECS Dept. ACAL Lab
Ann Arbor, MI 48109-2122
Ph: 7349362828 or 7347098083
[email protected]
Research Interest:
Low Power circuit design: energy-efficient system design, wide range DVS (dynamic voltage scaling), subthreshold circuit analysis and optimization under process variation.
Current Research:
Analysis and optimization of subthreshold logic design under process variation: We investigate how to mitigate subthreshold process variation and make digital circuit more robust in subthreshold.
Wide range SRAM design: We are looking at new SRAM designs that can operate over a very wide voltage range.
Previous work: Dynamic voltage scaling (DVS) issues involved in low-power VLSI design. We investigated the difficulties in designing a DVS system and possible solutions to broaden the voltage range that a system can work at. Very interestingly, we found that it is, under some cases, desirable that a chip can scale down to sub-threshold voltage. Then we studied the minimum power efficient voltage when considering both dynamic and leakage power.
More recently, I am studying voltage scaling properties of different design styles. And for library based design, we are looking at the DVS capabilities of those pre-designed cells, then we can build a more DVS reliable library for ASIC design.