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Power supply noise increases the circuit delay, which may lead to performance failure of a design. Decoupling capacitance (decap) addition is effective in reducing the power supply noise, thus mak¬ing the supply network more robust in presence of large switching currents. Traditionally, decaps have been allocated in order to minimize the worst-case voltage drop occurring in the power grid. We developed an approach for timing-aware decap allocation which uses global timing slacks to drive the decap optimization. The approach is based on the observation that in a circuit, the non-critical gates with larger timing slacks can tolerate a relatively higher supply voltage drop as compared to the gates on the critical paths. The decap allocation is formulated as a non-linear optimization problem using Lagrangian relaxation, and modified adjoint method is used to efficiently obtain the sensitivities of objective function to decap sizes. A fast path-based heuristic was also implemented and compared with the global optimization formulation. Compared to uniformly allocated decaps, the proposed approach utilizes 35.5% less total decap to meet the same delay target. For the same total decap budget, the proposed approach is shown to improve the circuit delay by 10.1% on an average.
Publications:
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Sanjay Pant, David Blaauw, “Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks,” in ACM/IEEE International Workshop on Timing in Synthesis and Specification (TAU), February 2006. ©IEEE File: [PDF Document] Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Sanjay Pant, David Blaauw, “Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks,” ACM/IEEE Asia-Pacific Design Automation Conference (ASP-DAC), January 2006 ©IEEE File:
