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Primary Contact
Rajeev Rao <[email protected]>
Leakage current has become a stringent constraint in today’s processor designs in addition to traditional constraints on frequency. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency.We first develop a method to estimate the variation of leakage current due to both intra-die and inter-die gate length process variability. We derive an analytical expression to estimate the probability density function (PDF) of the leakage current for stacked devices found in CMOS gates. These distributions of individual gate leakage currents are then combined to obtain the mean and variance of the leakage current for an entire circuit. We also present an approach to account for both the inter- and intra-die gate length variations to ensure that the circuit leakage PDF correctly models both types of variation. Using this model, we then devise an integrated approach to accurately estimate the yield loss when both a frequency and power limits are imposed on a design.
Publications:
Analytical Yield Prediction Considering Leakage/Performance Correlation
Rajeev Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester, “Analytical Yield Prediction Considering Leakage/Performance Correlation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T-CAD), Vol. 25, Issue 9, September 2006, pg. 1685-1695 ©IEEE File: PDF Document]
Modeling and Analysis of Parametric Yield Under Power and Performance Constraints
Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan, “Modeling and Analysis of Parametric Yield Under Power and Performance Constraints,” IEEE Design and Test of Computers (D&T), Vol. 22, No. 4, July-August 2005, pg. 376-385. ©IEEE File: [PDF Document]
Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits
Rajeev Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester, “Statistical Analysis of Subthreshold Leakage Current for VLSI Circuits,” IEEE Transactions on Very Large Scale Integration Systems (T-VLSI), Volume 12, Issue 2, Feb. 2004, pg. 131 – 139. ©IEEE File: [PDF Document]
Parametric Yield Estimation Considering Leakage Variability
Rajeev Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester, “Parametric Yield Estimation Considering Leakage Variability,” ACM/IEEE Design Automation Conference (DAC), June 2004, pg. 442-447. Best Paper Nomination ©IEEE File [PDF Document]
Statistical Estimation of Leakage Current Considering Inter- and Intra-Die Process Variation
Rajeev Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester, “Statistical Estimation of Leakage Current Considering Inter- and Intra-Die Process Variation,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2003, pg. 84-89 ©IEEE File: [PDF Document]