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With increasing clock frequency and silicon integration achievable through aggressive process scaling, designers find it all the more difficult to meet the often conflicting constraints required to engineer low power and yet robust circuits. Traditionally, this has been achieved through designing for the worst-case combination of process, voltage and temperature conditions. Safety margins are added during design time to ensure that circuits operate correctly even in the worst-case. However, with increased process variability and design uncertainties, these safety margins often lead to overly conservative designs and contribute significantly to the overall power consumption of a processor.
Razor is a novel design methodology that eliminates the safety margins and uses self-checking mechanisms to ensure computational correctness in presence of errors. Thus, it represents a radical departure from the traditional design paradigm of “worst-case” and “always-correct” to “typical-case” and “usually-correct”. Using in situ error detection and correction mechanisms, a “Razor”-ed pipeline is able to dynamically adjust its supply voltage or frequency to operate at exact point of failure. In addition, it can also tune its system parameters to operate below this point of failure so as to achieve a targeted error-rate.
Since its inception in 2003, Razor has constantly evolved over the years.
In the RazorI approach, speedpath failures are detected within a Razor flip-flop using the concept of temporal redundancy i.e by sampling an input data at two different points in time. The first sample is the speculative sample which is validated against a “always correct” delayed sample. This is implemented by critical-path flip-flops in the design are augmented with a so-called “shadow” latch which samples off the negative edge of the clock. We require an additional metastability-detector which detects and flags occurences of metastability at the output of the main flip-flop.
We demonstrated this idea in a 64 bit processor executing a subset of the ALPHA instruction set. We were able to demonstrate correct operation through Razor recovery in presence of errors even under over-scaled voltage levels. By operating at 0.1% error-rate, we were able to obtain about 50% energy savings over the worst-case at 120MHz.
The Razor I team:
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PhD Student: Shidhartha Das
Prototype development team: Shidhartha Das and Sanjay Pant
Prototype testing team: Shidhartha Das and David Roberts
Professors: Profs. David Blaauw, Trevor Mudge, Todd Austin (ACAL faculty) and Dr. Krisztian Flautner (ARM Ltd., UK)
Publications:
A Self-Tuning DVS Processor using Delay-Error Detection and Correction
Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David Blaauw, Todd Austin, Krisztián Flautner, Trevor Mudge, “A Self-Tuning DVS Processor using Delay-Error Detection and Correction,” IEEE Journal of Solid-State Circuits (JSSC), April 2006, pg. 792-804, invited paper ©IEEE [PDF]
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation
Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd Austin, Trevor Mudge, Nam Sung Kim, Krisztian Flautner, “Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation”, IEEE, Vol. 24, No. 6, November-December 2004, pg. 10-20. ©IEEE [PDF]
A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction
Shidhartha Das, David Roberts, Seokwoo Lee, Sanjay Pant, David Blaauw, Todd Austin, Trevor Mudge, Kris Flautner, “A Self-Tuning Dynamic Voltage Scaled Processor Using Delay-Error Detection and Correction”, Integrated Circuit Design and Technology, 2006 ICICDT ’06. 2006 IEEE International Conference on 24-26 May 2006 Page(s): 1-4 INVITED PAPER ©IEEE [PDF]
Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming
Seokwoo Lee, Todd Austin, Trevor Mudge, David Blaauw, “Reducing Pipeline Energy Demands with Local DVS and Dynamic Retiming,” ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), August 2004, pg. 319-324. [PDF]
Circuit-Aware Architectural Simulation
Seokwoo Lee, Shiddartha Des, Valeria Bertacco, Todd Austin, David Blaauw, Trevor Mudge, “Circuit-Aware Architectural Simulation,” ACM/IEEE Design Automation Conference (DAC), June 2004, pg. 305-310 ©IEEE [PDF]
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Toan Pham, Rajeev Rao, Conrad Ziesler, David Blaauw, Todd Austin, Trevor Mudge, “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation,”ACM/IEEE International Symposium on Microarchitecture (MICRO), December 2003, pg. 7-18. Best Paper Award ©IEEE [PDF]
Presentations:
Architectural Techniques for Adaptive Computing
“Architectural Techniques for Adaptive Computing”, David Blaauw, Shidhartha Das, Trevor Mudge, International Solid-State Circuits Conference, 2007
Razor: Dynamic Voltage Scaling Based on Timing Speculation
“Razor: Dynamic Voltage Scaling Based on Timing Speculation,” Gigascale Systems Research Center review meeting, San Jose, September 2003.